| contributor |
Naviner, Lirida
|
| Danger, Jean Luc
|
| Guilley, Sylvain
|
| Polti, Alexis
|
| Mathieu, Yves
|
| Mathérat, Philippe
|
| Graba, Tarik
|
| creator |
Mathieu, Yves
|
| date |
2005-12-07
|
| |
| description |
Boolean logic and sequential logic will be successively covered to arrive at machines with synchronous states on which most digital integrated circuits are based (microprocessors, programmable logic circuits, signal processing circuits, ...). Finally, a performance model (processing speed) of the logic will be built based on a simple model of simple technological model.
|
| Overall objective:
Understanding:
- the methods and concepts required to make integrated digital systems,
- the notion of performance of these systems, with the link between the virtual world of boolean logic (the models) and the hardware (the technology).
Operational objective: knowing how to analyse and design the logic architecture of a "small" microprocessor.
Cultural objective: from the notion of performance, among others, understanding the evolutions in this field.
The methods and concepts used in architecture of digital circuits will be both presented and practised, especially during obligatory practical exercises. In fact, if it is not impossible, in certain conditions, to carry out certain work at home, it is impossible to take measuring rigs and the models needed to learn with practice. Therefore each absence (that is not validated by the Initial Training Management) of a student will lead to 1 point being deducted from the score of the ENI Module of each student. Each practical exercise session lasts 2 TH (2 times 90 min. separated by a break of 15 min).
|
| Level: Licence 3ème année
|
| Level: Ingénieur 1ère année
|
| Course: Ingénieur
|
| Duration of the course: 30h00
|
| format |
text/html
|
| identifier |
ENST_ELEC102
|
| language |
en
|
| publisher |
Institut Télécom
|
| rights |
http://formation.enst.fr/licences/prive.html |